PIC16F723A-I/SS【PDF 101/286 页】MCU PIC 7KB FLASH XLP 28-SSOP

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Sheet目录3893

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2010-2012 Microchip Technology Inc.

DS41417B-page 19

PIC16(L)F722A/723A

TABLE 2-1:

PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Page

Bank 0

00h(2)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

26,34

01h

TMR0

Timer0 Module Register

xxxx xxxx

99,34

02h(2)

PCL

Program Counter (PC) Least Significant Byte

0000 0000

25,34

03h(2)

STATUS

IRP

RP1

RP0

ZDC

0001 1xxx

22,34

04h(2)

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

26,34

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xxxx xxxx

48,34

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

57,34

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

67,34

09h

PORTE

—

—RE3

—

---- xxxx

74,34

0Ah(1, 2)

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

25,34

0Bh(2)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

40,34

0Ch

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

43,34

0Dh

PIR2

—

CCP2IF

---- ---0

44,34

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

108,3 4

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

108,3 4

10h

T1CON

TMR1CS1 TMR1CS0 T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

—TMR1ON

0000 00-0

112 ,34

11h

TMR2

Timer2 Module Register

0000 0000

115 ,34

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1 T2CKPS0 -000 0000

116 ,34

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

157,3 4

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

174,3 4

15h

CCPR1L

Capture/Compare/PWM Register (LSB)

xxxx xxxx

125,3 4

16h

CCPR1H

Capture/Compare/PWM Register (MSB)

xxxx xxxx

125,3 4

17h

CCP1CON

—

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

124,3 4

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

143,3 4

19h

TXREG

USART Transmit Data Register

0000 0000

142,3 4

1Ah

RCREG

USART Receive Data Register

0000 0000

140,3 4

1Bh

CCPR2L

Capture/Compare/PWM Register 2 (LSB)

xxxx xxxx

125,3 4

1Ch

CCPR2H

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx

125,3 4

1Dh

CCP2CON

—

DC2B1

DC2B0

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

124,3 4

1Eh

ADRES

A/D Result Register

xxxx xxxx

93,34

1Fh

ADCON0

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

--00 0000

92,34

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

Accessible only when SSPM<3:0> = 1001.

Accessible only when SSPM<3:0>

1001.

This bit is always ‘1’ as RE3 is input only.

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